In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. As the size of CMOS transistors, also referred to as MOSFETs, are scaled down, one of the most important challenges facing a device designer are short channel effects (SCE) in reduced gate length devices. For example, short channel effects that influence the electrical operating characteristics of CMOS devices include VT rolloff, drain induced barrier lowering (DIBL), and subthreshold swing degradation. Short channel effects (SCE) are a function of several processing effects including width and depth of S/D regions and S/D region dopant concentration.
For example, since a characteristic VT rolloff length is related to the junction depth (xj), shallower junction (S/D region) depths can improve device operating characteristics. However, an off-setting consideration is the increase in the S/D parasitic resistance which has several components including the resistance of the source/drain extension (SDE) region and the resistance of salicide portions over the source/drain regions. As the junction depth decreases to reduce SCE, S/D parasitic resistances may increase thereby degrading device performance.
To overcome some of the short channel effects (SCE) effects as device sizes are scaled down, including leakage current (diode leakage), proposed solutions have included providing raised S/D regions by raising up the S/D contact surface by selective epitaxial silicon growth (SEG) over the S/D contact regions. While diode leakage has been shown to be reduced by this process, other shortcomings remain, including achieving shallower junction depths while preserving a low S/D resistance and reducing overlap capacitance between the S/D regions and the channel region underlying the gate structure. For example, Gate to drain overlap capacitance has important implications in both analog and digital applications including high frequency applications. Gate to drain overlap capacitance is strongly affected by lateral diffusion of the doped S/D regions, which is increasingly difficult to control by thermal processes. For example, carrying out a process to form raised S/D structures following doping of the S/D regions contributes an additional thermal process which can undesirably increase the lateral diffusion thereby increasing gate to drain overlap capacitance and degrading device performance.
There is therefore a continuing need in the MOSFET device design and processing art to develop new device designs and processing methods for forming MOSFET devices to achieved reduced short channel effects (SCE) while avoiding degradation of device performance including overlap capacitance.
It is therefore among the objects of the present invention to provide an improved MOSFET device and a process for forming the same to achieved reduced short channel effects (SCE) while avoiding degradation of device performance including overlap capacitance in addition to overcoming other shortcomings of the prior art.